A circuit pattern made of a thin film of a metal or an insulating material on a substrate has hitherto been used in every electronic circuits which are used in computers, communications, information home appliances, various display devices and the like. Further, in order to make it compatible with a rapidly progressing advanced information society, higher integration (realization of high definition) is demanded.
For the formation of such a circuit pattern, a method using a photolithography etching process has been generally adopted. A representative process of this method is illustrated in FIGS. 10 to 11. As illustrated in FIGS. 10 to 11, this method is a method in which after forming a thin film for forming a circuit pattern in at least a part of the surface of a substrate, a resist is coated and dried to form a resist layer. Then, by exposing the resist layer via a mask and developing it, a pattern (inverse circuit pattern) which is inverse to the circuit pattern is formed. Thereafter, a desired circuit pattern is formed through etching and removal of the resist layer. This method is excellent in view of mass productivity because precision of pattern formation is good, the same pattern can be reproduced over and over, and a plural number of electronic circuits can be formed on the same substrate.
However, as illustrated in FIGS. 10 to 11, this method using a photolithography etching process is a method in which a circuit pattern of an electronic circuit is accomplished by repeating a number of steps. According to the method illustrated in FIGS. 10 to 11, after forming a thin film layer 51 on a substrate 50 (FIG. 10(b)), a resist layer 52 is formed (FIG. 10(c)); exposure, development treatment, etching and peeling off of the resist layer 52 are carried out (FIGS. 10(d) to 10(e) and FIG. 11(a)); and furthermore, after forming an insulating layer 53 (FIG. 11(b)), formation of a resist layer 54, exposure, development, etching and peeling off of the resist layer 54 are carried out (FIGS. 11(c) to 11(e)).
That is, in this method, every time when forming a circuit pattern comprising a thin film layer and an insulating layer, a very large number of steps as many as 22 steps, which include film formation, resist coating, drying, exposure, development, etching, resist layer peeling off and the like, are required. For that reason, there was involved a problem that the manufacturing cost is very high. Furthermore, in this method, every time when performing the foregoing number of steps, a large amount of a developing solution, a chemical solution such as an etchant, etc. and a washing solution are used. This involved not only problems that the yield is low and the manufacturing cost is very high, but also involved a problem that an environmental load such as a treatment of waste fluid, an aspect of which is an important matter of concern nowadays, is very large.
Then, there has been proposed a lift-off method which has a small number of steps and gives a low environmental load as compared with the foregoing photography etching process (see, for example, Patent Documents 1 to 7).
In general, the lift-off method is a method in which an inverse circuit pattern is formed by a resist layer on a substrate; a thin film layer is formed on the surface of the substrate; and subsequently, the resist layer is peeled off, thereby forming a circuit pattern by the thin film layer in an opening of the resist layer. FIGS. 12 to 13 illustrate steps of forming an inverse circuit pattern of a resist layer by carrying out exposure, development and the like of the resist layer; and this illustrates steps of a wet lift-off method which is carried out under a so-called wet condition.
In the method illustrated in FIGS. 12 to 13, a resist layer 62 is formed on a substrate 61 (FIG. 12(b)); and a resist pattern is formed by exposure and development (FIGS. 12(c) to 12(d)). Thereafter, after forming a thin film layer 63, the unnecessary resist layer 62 and thin film layer 63 are peeled off (FIG. 12(e) and FIG. 13(a)). Furthermore, a resist layer 64 is again formed on the substrate 61, a resist pattern is formed by exposure and development, and an insulating layer 65 is formed (FIGS. 13(b) to 13(c)); and thereafter, the unnecessary resist layer 64 and insulating layer 65 are peeled off (FIG. 13(d)).
Then, in such a lift-off method, in order to form a desired fine pattern in high precision, a cross-sectional shape of the opening to be formed in the resist layer is important. There is proposed a method of forming a pattern in which the cross-sectional shape is specifically made into an inverse tapered shape, an overhang shape, a double-layer lamination type or a T-shape type (see Patent Documents 8 to 12).    Patent Document 1: Japanese Patent No. 2989064    Patent Document 2: Japanese Patent No. 3028094    Patent Document 3: JP-A-7-168368    Patent Document 4: JP-A-8-315981    Patent Document 5: JP-A-11-317418    Patent Document 6: JP-A-2002-134004    Patent Document 7: JP-A-11-339574    Patent Document 8: JP-A-56-81954    Patent Document 9: JP-A-1-236658    Patent Document 10: JP-A-7-29846    Patent Document 11: JP-A-2003-287905    Patent Document 12: JP-A-9-211868